1. Field of the Invention
The field of the present invention relates generally to electronic systems where accurate and stable signal edge placement is required. More particularly, the present invention relates to a psuedo-NMOS fine/coarse wired-or tapped delay line having both fine and coarse discrete delay elements connected serially.
2. Related Art
Many conventional discrete and gate array devices are used in the electronics industry for adjusting the phase of digital signals. Such phase adjustment is typically accomplished by delaying the rising or falling edge of the digital pulses. Examples of such discrete devices are described in U.S. Pat. No. 4,947,064 to Kim, U.S. Pat. No. 4,899,071 to Morales, and U.S. Pat. No. 4,806,804 to O'Leary. All teach circuits to implement such delays. An implementation of a delay circuit for gate array LSI is taught by U.S. Pat. No. 4,700,089 to Fujii, et al.
However, due to the power supply, temperature, and manufacturing process variations the discrete amounts of delay produced by the conventional circuits can vary. Such inaccuracies are acceptable in most general applications of the delay elements, but are unacceptable for systems such as testing and calibrations systems.